The present invention relates to semiconductor devices having accurately dimensioned interconnection patterns. The present invention is particularly applicable to ultra large-scale integrated circuit (ULSI) devices having features in the deep sub-micron regime.
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it has become increasingly difficult to satisfy the requirements for dimensional accuracy, particularly in integration technology which is considered one of the most demanding aspects of fabricating ULSI devices. Demands for ULSI semiconductor wiring require increasingly denser arrays with minimal spacings between narrower conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.12 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a patterned conductive layer comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. The excess conductive material or overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-a-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein a first dielectric layer, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low dielectric constant material, i.e., a material having a dielectric constant of no greater than 4 (with a dielectric constant of 1 representing a vacuum), is formed over an underlying pattern having a capping layer thereon, e.g., a Cu or Cu alloy pattern with a silicon nitride capping layer. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
In implementing conventional damascene techniques an organic bottom anti-reflective coating (BARC) is typically deposited over the underlying capped metal feature. In implementing dual damascene techniques wherein the via is formed before forming the trench (via first-trench last), a middle etch stop layer, such as silicon nitride or silicon oxynitride, is deposited on the first dielectric layer. A second dielectric layer is then deposited on the middle etch stop layer. The etch stop layer is chosen for its high selectivity with respect to the overlying second dielectric layer. A photoresist mask is then formed over the second dielectric layer, and anisotropic etching is conducted to form a via opening through the second dielectric layer, middle etch stop layer and first dielectric layer. Subsequently, the photoresist mask for the via opening is removed and a photoresist mask for a trench is formed overlying the second dielectric layer. The second photoresist mask is typically formed at a thickness of about 4,000 xc3x85 to about 6,000 xc3x85, which is undesirably large yielding less accurate patterning than a relatively thinner photoresist mask. However, such a large thickness is required due to photoresist consumption during patterning and etching, because of the relatively poor ability of the middle etch stop layer, e.g., silicon oxynitride, to also function as an anti-reflective coating (ARC) Anisotropic etching is then conducted to form a trench, having a width greater than the diameter or cross sectional width of the via hole, stopping on the middle etch stop layer.
As miniaturization proceeds apace with an attendant shrinkage in the size of metal lines, e.g., metal lines having a width of about 0.3 micron and under, e.g., about 0.2 micron and under, it becomes increasingly difficult to maintain the dimensional accuracy of the metal lines, particularly when implementing dual damascene techniques. Accordingly, there exists a need for interconnection methodology enabling the formation of metal features, such as metal lines, with high dimensional accuracy. There exists a particular need for dual damascene methodology enabling the formation of accurately dimensional metal lines having a width of about 0.3 micron and under, e.g., about 0.2 micron and under.
An advantage of the present invention is a semiconductor device comprising an interconnection pattern with high dimensional accuracy.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising an interconnection pattern with accurately dimensioned metal lines.
Additional advantages and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer on a capping layer overlying a lower metal feature of a lower metal level; forming a silicon carbide etch stop layer/anti-reflective coating (ARC) on the first dielectric layer; forming a second dielectric layer on the silicon carbide etch stop layer/ARC; and etching to form an opening, having a cross sectional width, through the second dielectric layer, through the silicon carbide etch stop layer/ARC and through the first dielectric layer exposing a portion of the capping layer.
Embodiments of the present invention comprise forming a photoresist mask on the second dielectric layer at a thickness of about 2,500 xc3x85 to about 3,500 xc3x85, e.g., about 3,000 xc3x85, and etching to form a trench having a width greater than the cross sectional width of the first opening through the second dielectric layer stopping on the silicon carbide etch stop layer/ARC, and etching through the exposed portion of the underlying capping layer, e.g., silicon nitride, exposing a portion of the lower metal feature. Embodiments of the present invention further include chemical vapor depositing silicon carbide having an extinction coefficient (k) of about xe2x88x920.10 to about xe2x88x920.60, as the middle etch stop layer/ARC. After depositing a suitable barrier metal layer and seedlayer, Cu or Cu alloy is then deposited, as by electrodeposition or electroless deposition. CMP is then conducted followed by deposition of a suitable capping layer, such as silicon nitride. As employed throughout this disclosure, the symbol Cu is intended to encompass high purity elemental copper as well as Cu-based alloys, such as Cu alloys containing minor amounts of tin, zinc, manganese, titanium, germanium, zirconium, strontium, palladium, magnesium, chromium and tantalum.
Another aspect of the present invention is a semiconductor device comprising an interconnection pattern comprising: a lower metal level comprising a lower metal feature with a capping layer thereon; a first dielectric layer on the capping layer; a silicon carbide etch stop layer/ARC on the first dielectric layer; a second dielectric layer on the silicon carbide etch stop layer/ARC; and a dual damascene structure comprising: a metal line, such as Cu or a Cu alloy, in the second dielectric layer and on a portion of the silicon carbide etch stop layer/ARC; and a via in the first dielectric layer, wherein the via is in electrical contact with the lower part of the metal line and in electrical contact with an upper part of the lower metal feature.
Embodiments of the present invention comprise a semiconductor device with a middle silicon carbide etch stop layer/ARC having an extinction coefficient (k) of about xe2x88x920.10 to about xe2x88x920.60 and a thickness of about 200 xc3x85 to about 800 xc3x85.